1. Technical Field
Embodiments described herein relate to integrated circuit layouts and designs. More particularly, embodiments described herein relate to the use of multi-bit flip-flops in the integrated circuit layouts and designs and methods for assessing timing slack properties of the multi-bit flip-flops and organizing individual flip-flops within the multi-bit flip-flops for use in the integrated circuit layouts and designs.
2. Description of Related Art
Multiple bit (multi-bit) flip-flops (flip-flops with 2, 4, or even 8 bits per flop) and/or other multi-bit clocked storage devices are commonly used in current low power integrated circuit (IC) designs to primarily lower clock dynamic power (clock switching power). Multi-bit flip-flops (multi-bit flops) reduce clock dynamic power by implementing multiple individual flip-flops in a single large flip-flop with shared clock circuitry. Multi-bit flops are introduced using logic synthesis tools with multiple sequential states being mapped to each multi-bit flop (for example, depending on whether it is 2, 4, or 8 bits). During physical design (place and route), the timing slacks on each of the input and output pins of multi-bit flops can be vastly different.
Useful clock skewing is a well known method of adjusting the clock latencies to flip-flops (either delaying or advancing the clock) to help improve the speed of the IC design (for example, by rebalancing/redistributing timing slack across flip-flops). There should be timing slack on at least one (either input or output) side of a flip-flop to perform useful clock skewing. When multi-bit flops are present, the opportunity to perform useful clock skewing is limited by the difference in timing slack between the data (input) and its corresponding output pin timing slacks for multiple bits across the flip-flop. By adjusting the clock going into multi-bit flops, slacks for multiple input-output pin pairs are affected.
The cell size for multi-bit flops are primarily determined by the worst timing slack on any of the input (for setup) or output (for launch path) pins and by the drive strength required for the worst load on any of the multi-bit flop's output pins. The cell size of multi-bit flops determine sequential and clock power. Therefore, reducing multi-bit flop cell sizes may help reduce overall power significantly.
When a single-bit flip-flop is driving a large load (fanout), the single-bit flip-flop is typically upsized to drive the large load. Sequential duplication (flip-flop duplication) is typically used to split the large load between multiple the flip-flops. In sequential duplication, the single-bit flip-flop is replicated and the total load is distributed between the duplicate single-bit flip-flops (either based on load or timing slack). When single-bit flip-flops are duplicated in such a manner, the clock power needed increases since multiple clock fanout points are introduced in the IC design. Thus, higher switching clock power and larger clock drivers are need to drive the duplicate single-bit flip flops and the large load.